Method and system for driving light emitting display

ABSTRACT

A display system includes a driver for operating a panel having a plurality of pixels arranged by a plurality of first lines and at least one second line The driver includes a driver output unit for providing to the panel a single driver output for activating the plurality of first lines, the single driver output being demultiplexed on the panel to activate each first line.

FIELD OF INVENTION

The present invention relates to a display system, more specifically toa method and system for driving light emitting displays.

BACKGROUND OF THE INVENTION

A display device having a plurality of pixels (or subpixels) arranged ina matrix has been widely used in various applications. Such a displaydevice includes a panel having the pixels and peripheral circuits forcontrolling the panels. Typically, the pixels are defined by theintersections of scan lines and data lines, and the peripheral circuitsinclude a gate driver for scanning the scan lines and a source driverfor supplying image data to the data lines. The source driver mayinclude gamma corrections for controlling gray scale of each pixel. Inorder to display a frame, the source driver and the gate driverrespectively provide a data signal and a scan signal to thecorresponding data line and the corresponding scan line. As a result,each pixel will display a predetermined brightness and color.

In recent years, the matrix display has been widely employed in smallelectronic devices, such as handheld devices, cellular phones, personaldigital assistants (PDAs), and cameras. However, the conversional schemeand structure of the source driver and the gate driver demands the largenumber of elements (e.g., resistors, switchers, and operationalamplifiers), resulting that the layout area of the peripheral circuitsis still large and expensive.

Therefore there is a need to provide a display driver that can reduce adriver die area and thus cost, without reducing the driver performance.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a method and system thatobviates or mitigates at least one of the disadvantages of existingsystems.

According to an embodiment of this disclosure, there is provided adisplay system, which includes: a driver for operating a panel having aplurality of pixels arranged by a plurality of first lines and at leastone second line, the driver having: a driver output unit for providingto the panel a single driver output for activating the plurality offirst lines, the single driver output being demultiplexed on the panelto activate each first line.

According to an embodiment of this disclosure, there is provided adisplay system, which includes: a driver for operating a panel having aplurality of pixels arranged by a plurality of data lines and at leastone scan line, the driver having: a shift register unit including aplurality of shift registers; a latch and shift register unit includinga plurality of latch and shift circuits for the plurality of shiftregisters, each storing an image signal from the corresponding shiftregister or shifting the image signal to a next latch and shift circuit;and a decoder unit including at least one decoder coupled to one of thelatch and shift circuits, for decoding the image signal latched in theone of the latch and shift circuit to provide a driver output.

According to an embodiment of this disclosure, there is provided adisplay system, which includes: a driver for operating a panel having aplurality of pixels, the driver having: a plurality of multiplexers fora plurality of offset gamma curve sections, each offset gamma curvesection having a first range less than a second range of a main gammacurve, at least one of offset gamma curve sections being offset by apredetermined voltage from a corresponding section of the main gammacurve; a plurality of decoders for the plurality of multiplexers; and anoutput buffer for providing a driver output based on the output from thedecoder and the predetermined voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will become more apparent fromthe following description in which reference is made to the appendeddrawings wherein:

FIG. 1A illustrates a gate driver and a panel for a display system;

FIG. 1B illustrates an example of the gate driver and the panel of FIG.1A;

FIG. 2 illustrates a timing chart for operating the display system ofFIGS. 1A-1B;

FIG. 3A illustrates another example of a gate driver and a panel for adisplay system;

FIG. 3B illustrates an example of the gate driver and the panel of FIG.3A;

FIG. 4 illustrates a timing chart for operating the display system ofFIGS. 3A-3B;

FIG. 5 illustrates an example of a source driver and a panel for adisplay system;

FIG. 6 illustrates an example of operation for the display system havingRGB pixel structure;

FIG. 7 illustrates a further example of a source driver and a panel fora display system;

FIG. 8 illustrates a further example of a source driver and a panel fora display system having RGBW pixel structure;

FIG. 9 illustrates an example of subpixel configuration for RGBW pixelstricture;

FIG. 10 illustrates a further example of a source driver, external gammaand a panel for a display system;

FIG. 11 illustrates a further example of a source driver and a panel fora display system;

FIG. 12 illustrates a further example of a source driver and a panel fora display system;

FIG. 13 illustrates a source driver for a conventional display system;

FIG. 14 illustrates a further example of a source driver for a displaysystem;

FIG. 15 illustrates a further example of a source driver for a displaysystem;

FIG. 16 illustrates an example of a gamma curve and segmented offsetgamma curves;

FIG. 17 illustrates an example of a display system having the gatedriver of FIG. 1A or 3A;

FIG. 18 illustrates an example of a display system having the sourcedriver of FIGS. 5-12; and

FIG. 19 illustrates an example of a display system having the sourcedriver of FIGS. 14-15.

DETAILED DESCRIPTION

One or more currently preferred embodiments have been described by wayof example. It will be apparent to persons skilled in the art that anumber of variations and modifications can be made without departingfrom the scope of the invention as defined in the claims.

Embodiments in this disclosure are described using a panel having pixelsthat are coupled to at least first line and at least one second line(e.g., scan lines and data lines) and being operated by a driver. Thedriver may be a driver IC having a plurality of pins, e.g., sourcedriver ICs, gate driver ICs. The panel may be, for example, but notlimited to, a LCD or LED panel. The panel may be a color panel or amonochrome panel.

In the description below, the terms “source driver” and “data driver”are used interchangeably, and the terms “gate driver” and “addressdriver” are used interchangeably. In the description below, the terms“row”, “scan line” and “address line” may be used interchangeably. Inthe description below, the terms “column”, “data line” and “source line”may be used interchangeably. In the description below, the terms “pixel”and “subpixel” may be used interchangeably.

Referring to FIGS. 1A-1B, there is illustrated a system 100 having agate driver 102 and a panel 110 having pixels arranged in rows andcolumns. The system 100 includes a mechanism for multiplexing (muxing)gate driver outputs based on frequency reduction. In FIG. 1A, “fv”represents the vertical frequency of the display (or row frequency), and“M” is the number of muxing blocks. In FIG. 1B, “Cell #i” represents anaddress cell 106, and “SEL k” (k=(i−1)*M+1, (i−1)*M+2, . . . ,(i−1)*M+M+1, i*M) represents a row or a scan line coupled to the row ofthe panel 110. A pixel in the row is selected by the scan line. Theaddress cell 106 may be a logic or a flip-flop in a shift register chainto output a gate output.

The gate driver 102 includes a driver output unit 104 having at leastone address cell 106 (Cell #i). The address cell 106 provides a singlegate driver output 108 which is shared by M rows. An individual gatedriver output 108 from the gate driver 102 is active for M rows. On thepanel side 110, a demultiplexer 112 (“1:M Demuxs” in FIG. 1A) isemployed for M rows. The input of the demultiplexer 112 is coupled tothe gate driver output 108, and the outputs of the demultiplexer 112 arecoupled to M rows. In this example, the demultiplexer 112 is coupled toscan lines SEL (i−1)*M+1, SEL (i−1)*M+2, . . . , and SEL i*M. Theactivated gate driver output 108 from the address cell 106 (Cell #i) isassigned to each individual row in sequence, via the demultiplexer 112.

The demultiplexer 112 is implemented using, for example, thin filmtransistors, on the panel 110. The demultiplexer 112 includes aplurality of switch blocks for activating M rows. In FIG. 1B, switches116 (SET #1, SET #2, . . . , SET #M) are shown as an example of thecomponents of the demultiplexer 112. The switch block 116 (SET #k: k=1,2, . . . , M) is employed for the scan line SEL (i−1)*M+k. Each switchblock 116 includes a pair of switches, one being capable of connectingthe gate driver output 108 to the corresponding scan line and the otherbeing capable of connecting VGL to the corresponding scan line. VGL maybe a ground level voltage. Each scan line SEL (i−1)*M+k turns to be onthe VGL level or the activated gate driver output 108 via thecorresponding switch block 116 (SET #k). Each switch block 116 (SET #k)is controlled by the corresponding control signal CTRL (k). In FIG. 3B,the scan line SEL (i−1)*M+k is selected (becomes active) by the controlsignal CTRL (k). By operating the demultiplexer 112 with the controlsignals CTRL (1)-CTRL (M), the number of the gate driver outputs andaddress cells is reduced by a factor of M.

In FIG. 1B, one address cell 116 is shown as an element of the driveroutput unit 104; however, the number of the address cells may vary. InFIG. 1B, M rows (scan lines) are shown; however, the panel 110 mayinclude a plurality of groups of rows where the ith group has M rows andis operated by the ith address cell (Cell #i). One of ordinary skill inthe art would appreciate that the gate driver 102 and the panel 110 mayinclude components not shown in the FIGS. 1A-1B.

Referring to FIGS. 1A, 1B and 2, the operation of a display having thegate driver 102 and the panel 110 is described. Each of the controllingsignals CTRL (1)-CTRL (M) for controlling the demultiplexing on thepanel 110 works at the normal gate frequency. When the displayprogramming reaches the row SEL (i−1)*M+1, the control signal CTRL (1)for that row is high, resulting that the address cell 106 for the ithblock (Cell #i) of rows is connected to SEL (i−1)*M+1. Thus, that rowSEL (i−1)*M+1 is selected and the image data can be written in thepixels of the row.

After the programming of the row SEL (i−1)*M+1, the next control signalCTRL (2) is high, resulting that the next row SEL (i−1)*M+2 becomesactive. This continues till the entire display is programmed (end of aframe).

If a row is not active, the control signal related to that row is low orthe address cell related to that row is not active. Thus, the row isconnected to VGL which will disconnect the pixels in that row from thegate driver 102.

Referring to FIGS. 3A-3B, there is illustrated a system 130 having agate driver 132 and a panel 140 having pixels arranged in rows andcolumns. The system 130 has a mechanism for reducing the number of gatedriver outputs and reducing the operation frequency of demultiplexingcontrol signals on the panel side. In FIG. 3A, “fv” represents thevertical frequency of the display (or row frequency). In FIG. 3B, “Cell#j” (j=i, i+1, i+2, i+3) represents an address cell, and “SEL k” (k=i,i+1, i+2, i+3) represents a row or a scan line coupled to the row of thepanel 140. A pixel in the row is selected by the scan line. The addresscell may be a logic or a flip-flop in a shift register chain to output agate output.

In the system 130, gate driver output signals are multiplexed on thegate driver 132 side, and the outputs from the gate driver 132 aredemultiplexed on the panel 140 side.

The gate driver 132 includes a driver output unit 133 having a pluralityof multiplexers for a plurality of address cells. Each address cellprovides a gate driver signal, and each multiplexer multiplexing thegate driver signals and outputs a single gate driver output. In FIG. 3B,four address cells 138a-138d (Cell #i, Cell #i+1, Cell #i+2, and Cell#i+3) are shown as an example of the address cells in the gate driver132. In FIG. 3B, two multiplexers 134a and 134b are shown as an exampleof multiplexing the gate driver signals. The multiplexers 134a and 134bare controlled by a control signal iCTRL. The multiplexer 134a iscoupled to the address cells 138a and 138c (Cell #i and Cell #i+2) andoutputs a gate output signal 136a that corresponds to either addresscell 138a or 138c (Cell #i or Cell #i+2). The multiplexer 134b iscoupled to the address cells 138b and 138d (Cell #i+1 and Cell #i+3) andoutputs a gate output signal 136b that corresponds to either addresscell 138b or 138d (Cell #i+1 or Cell #i+3).

The panel 140 includes a multiplexer 142 (“1:M Demuxs” in FIG. 3A)coupling to the gate driver outputs and a plurality of rows. Thedemultiplexer 142 is implemented using, for example, thin filmtransistors, on the panel 140. The demultiplexer 142 includes aplurality of switch group blocks, each coupling to the gate drivermultiplexers. In FIG. 3B, two switch group blocks 146a and 146b (SET #1and SET #2) are shown as an example of the components of thedemultiplexer 142. On the panel side 140, the activated gate driveroutputs 136a and 136b are assigned of the switch group blocks 146a and146b.

Each switch group block in the panel 140 includes a plurality of switchblocks 148. In FIG. 3B, each of the switch group blocks 146a and 146bincludes two switch blocks 148, one being capable of coupling one gatedriver output 136a to one scan line and the other being capable ofcoupling the other gate driver output 136b to the other scan line. Theswitch block 148 includes a pair of switches, one being capable ofcoupling the gate driver output to the corresponding scan line and theother being capable of coupling VGL to the corresponding scan line. VGLmay be a ground level voltage. The switch block 148 in the switch groupblock (SET #k: k=1, 2, . . . ) is controlled by the correspondingcontrol signal CTRL (k). Each scan line turns to be on the VGL level orthe corresponding activated gate driver output 136a or 136b via thecorresponding switch block 148. In FIG. 3B, the scan lines SEL (i) andSEL (i+1) are selected (become active) by the control signal CTRL (1),and the scan lines SEL (i+2) and SEL (i+3) are selected (become active)by the control signal CTRL (2).

In FIG. 3B, the multiplexing (muxing) and demultiplexing (demuxing)operations are executed for two rows, however, the multiplexing anddemultiplexing operations may be executed for more than two rows. InFIG. 3B, four address cells are shown as an element of the driver outputunit 133; however, the number of the address cells is not limited tofour and may vary. In FIG. 3B, rows (scan lines) are divided into twogroups, each having two rows; however, the number of groups and thenumber of rows in each group are not limited to two and may vary. One ofordinary skill in the art would appreciate that the gate driver 132 andthe panel 140 may include components not shown in the FIGS. 3A-3B.

In this structure, the physical multiplexing is used at the gate driverside 132. As a result, the number of address cells remains the samewhile the number of gate driver outputs is reduced by a factor ofmultiplexing blocks. The number of rows in each set (SET #k) can beincreased for further reduction in output of the gate driver and thefrequency of the control signals. Since multiple gate driver outputs canbe active, the operation frequency of the demultiplexing control signalsis reduced.

Referring to FIGS. 3A, 3B and 4, the operation of a display having thegate driver 132 and the panel 140 is described. When the displayprogramming reaches the rows SEL (i) and SEL (i+1), the control signalCTRL (1) for those rows is high (150), resulting that the gate driveroutput 136a is coupled to the row SEL (i) and the gate driver output136b is coupled to the row SEL (i+1). At this period (150), the controlsignal iCTRL is in one state (e.g., low). The gate driver output 136acorresponds to the output from the address cell 138a (Cell #i) and thegate driver output 136b corresponds to the output from the address cell138b (Cell #i+1). The image data can be written in the pixels of theselected rows SEL (i) and SEL (i+1).

After the programming of the rows SEL (i) and SEL (i+1), the nextcontrol signal CTRL (2) is high (152), resulting that the next rows SEL(i+2) and SEL (i+3) become active. At this period (152), the controlsignal iCTRL is in the other state (e.g., high). The gate driver output136a corresponds to the output from the address cell 138c (Cell #i+2)and the gate driver output 136b corresponds to the output from theaddress cell 138d (Cell #i+3). The image data can be written in thepixels of the selected rows SEL (i+2) and SEL (i+3). This continues tillthe entire display is programmed (end of a frame).

If a row is not active, the control signal related to that row is low orthe address cell related to that row is not active. Thus, the row isconnected to VGL which will disconnect the pixels in that row from thegate driver 132.

Referring to FIG. 5, there is illustrated a system 160 having a sourcedriver 162 and a panel 180 having subpixels for RGB. Most of lightemitting displays employ different gammas (or gamma corrections) fordifferent subpixels, which use different decoders for different outputs.In the system 160, gammas (gamma corrections, gamma voltages) aremultiplexed on the source driver 162 side. In the description, the terms“gamma”, “gamma correction” and “gamma voltages” may be usedinterchangeably. One of ordinary skill in the art would appreciate thatthe source driver 162 and the panel 180 may include components not shownin FIG. 5.

The source driver 162 includes a driver output unit 164 having a CMOSmultiplexer 166 and a CMOS digital to analog converter (DAC) 170. Themultiplexer 166 multiplexes a Red gamma correction 168a, a Green gammacorrection 168b and a Blue gamma correction 168c. The DAC 170 includes adecoder. In the description, the terms “DAC” and “DAC decoder” may beused interchangeably.

Each of the gamma corrections 168a, 168b and 168c provides a referencevoltage to the DAC 170. The reference voltage is selected based on thedynamic range of the DAC decoder 170. The reference voltage at the gammacorrection block may be generated using, for example, resistors, or bestored using, for example, registers.

The output from the multiplexer 166 is provided to the DAC 170. Themultiple gammas share one decoder in the DAC 170. The DAC decoder 170operates on an output from a multiplexer 172. The multiplexer 172multiplexes a Red register (reg) 174a for storing image data for Red, aGreen register (reg) 174b for storing image data for Green, and a Blueregister (reg) 174c for storing image data for Blue. The CMOS DAC 170provides a single source driver output 174.

A demultiplexer 182 is employed on the panel 180 side to demultiplex thedriver output 174 from the source driver 162. The demultiplexer 182 isimplemented using, for example, thin film transistors, on the panel 180.The outputs from the demultiplexer 182 are couples to three data lines.The driver output 174 is demultiplexed 182 on the panel 180 side andgoes to different subpixels (i.e., Red subpixel, Blue subpixel and Greensubpixel).

In the system 160, the output of the source driver 162 is multiplexed toreduce the number of driver pins and demultiplexed at the panel 180. Tofurther improve the size of the driver area, the multiplexing isexecuted at few stage earlier at the gamma selection and DAC inputs. Forexample, when, the Red pixels are being programmed at the panel 180, theRed data (Red register 174a) and the red gamma 168a are assigned to theDAC 170.

The multiplexers 166 and 172 may be controlled by a color selectioncontrol signal ColorSel. The demultiplexer 182 may be controlled by thecontrol signal ColorSel or a control signal associated with themultiplexing control signal ColorSel.

As shown in FIG. 6, the Red pixels, Green pixels and Blue pixels may beprogrammed sequentially. It will be appreciated by one of ordinary skillin the art that the programming sequence is not limited to that of FIG.6, and is changeable by using the color selection control signal.

Generally, the output range of the voltage required for the lightemitting displays is high and thus source drivers are to be arail-to-rail design for the power. Currently, this results in usingmultiple CMOS decoders, leading to a larger area source driver.Referring to FIG. 7, there is illustrated a system 190 having a sourcedriver 192 and a panel 220 having subpixels for RGB. In this system 190,multiple gammas (gamma corrections, gamma voltages) are multiplexed anda DAC is divided into separate NMOS and PMOS components, resulting inthat the source driver 192 area is reduced. One of ordinary skill in theart would appreciate that the source driver 192 and the panel 220 mayinclude components not shown in FIG. 7.

The source driver 192 includes gamma corrections for Red, Blue andGreen, each providing a reference voltage to a DAC decoder. Thereference voltage is selected based on the dynamic range of the decoder.The reference voltage may be generated using, for example, resistors, orbe stored using, for example, registers. Each gamma correction has ahigh voltage level gamma correction (high voltage level of gammacorrections) and a low voltage level gamma correction (low voltage levelof gamma corrections). The high voltage level of gamma corrections is alevel from a predefined reference voltage to the high point of thedriver output, and the low voltage level of gamma corrections is a levelfrom the predetermined reference voltage to the beginning of the gammavoltage. The predetermined reference voltage may be at the middle forthe driver output range. For example, if the driver range is 10V, thepredetermined reference voltage is 5V; the high voltage level of gammacorrections is 5 to 10V; and the low voltage level of gamma correctionsis 0 to 5V.

The source driver 192 includes a driver output unit 194 having a PMOSmultiplexer 196 for the high voltage level of gamma corrections, and aNMOS multiplexer 200 for the low voltage level of gamma corrections. InFIG. 7, the multiplexer 196 multiplexes a high Red gamma correction198a, a high Green gamma correction 198b and a high Blue gammacorrection 198c, and the multiplexer 200 multiplexes a low Red gammacorrection 202a, a low Green gamma correction 202b and a low Blue gammacorrection 202c.

The driver output unit 194 includes a DAC that is divided into separatecomponents: a PMOS component 204 (“PMOS DAC” in FIG. 7) and a NMOScomponent 206 (“NMOS DAC” in FIG. 7). The PMOS component 202 includes aPMOS decoder and receives the output from the multiplexer 196. The NMOScomponent 206 includes a NMOS decoder and receives the output from themultiplexer 200. The reference voltage from the gamma correction isselected based on the dynamic range of the NMOS and PMOS decoders in thecomponents 204 and 206. The PMOS and NMOS decoders in the components 204and 206 operate on an output from a multiplexer 208 for multiplexing aRed register 210a, a Green register 210b, and a Blue register 210c. Theregisters 210a, 210b and 210c correspond to the resisters 174a, 174b and174c of FIG. 5, respectively. The multiplexers 196, 200 and 208 arecontrolled by a color selection control signal ColorSel.

The driver output unit 194 includes a CMOS multiplexer 212 formultiplexing the outputs from the PMOS and NMOS components 204 and 206.The multiplexer 212 is operated by an output from a multiplexer 214. Themultiplexer 214 multiplexes bit signals R[j], G[i], and B[k], based onthe color selection control signal ColorSel. R[j] (G[i], B[k]) is a bitthat defines when to use which part of the gamma for Red (Green, Blue).The bit R[j] (G[i], B[k]) is generated based on the Red register 210a(210b, 210c) and predefined data about the gamma curve for Red (Green,Blue), e.g., gamma values. The multiplexer 212 outputs a single sourcedriver output 216.

When the bit signal R[j] is active and the other signals are not active,the source driver 192 outputs the driver output 216 based on either thehigh Red gamma correction or the low Red gamma correction.

A demultiplexer 222 is employed on the panel 220 side to demultiplex thesource driver output 216. The demultiplexer 222 corresponds to thedemultiplexer 182 of FIG. 5. The demultiplexer 222 is implemented using,for example, thin film transistors, on the panel 220. The outputs fromthe demultiplexer 222 are couples to three data lines. The demultiplexer222 may be controlled by the control signal ColorSel or a control signalassociated with the multiplexing control signal ColorSel. Based on theoutput from the demultiplexer 222, one of three data lines is active.The driver output 216 is demultiplexed 222 on the panel 220 side andgoes to different subpixels (i.e., Red subpixel, Blue subpixel, Greensubpixel).

Based on the image data, one of the low gamma correction and the highgamma correction is selected. For example, if the high voltage level ofgamma corrections is 5 to 10V, the low voltage level of gammacorrections is 0 to 5V, and the image data requires 6 V, the high end ofgamma correction will be selected.

Based on the color selection control signal ColorSel, the Red pixels,Green pixels and Blue pixels may be programmed sequentially, similar tothat of FIG. 6. It will be appreciated by one of ordinary skill in theart that the programming sequence is not limited to that of FIG. 6, andis changeable by using the color selection control signal.

Instead of using a CMOS decoder that has twice as many transistors as aPMOS or NMOS decoder for the entire range the output voltage, the PMOSdecoder 204 is used for the higher range and the NOMS decoder 206 forthe lower range of the voltage. Thus, the area will be reduced by usingtwice less transistors.

Referring to FIG. 8, there is illustrated a system 230 having a sourcedriver 232 and a panel 270 having subpixels. The system 230 is appliedto quad RGBW pixel structure. Multiple gamma corrections for White,Green, Blue and Red are multiplexed in the source driver 232. In thesource driver 232, four different gamma corrections are generated(White, Green Blue and Low) for each of high voltage level and lowvoltage level. One of ordinary skill in the art would appreciate thatthe source driver 232 and the panel 270 may include components not shownin FIG. 8.

The source driver 232 includes gamma corrections for White, Green, Blueand Red, each providing a reference voltage to a DAC decoder. The gammacorrection may be generated using, for example, resistors, or be storedusing, for example, registers. Each gamma correction has a high voltagelevel gamma correction (high voltage level of gamma corrections) and alow voltage level gamma correction (low voltage level of gammacorrections). As described above, the high voltage level of gammacorrections is a level from the reference voltage to the referencevoltage to the high point of the driver output, and the low voltagelevel of gamma corrections is a level from the reference voltage to thebeginning of the gamma voltage.

The source driver 232 includes a driver output unit 270 having PMOSmultiplexers 240a and 240b for high voltage level of gamma corrections,and NMOS multiplexers 244a and 244b for low voltage level of gammacorrections. The multiplexer 240a multiplexes a high White gammacorrection 242a and a high Green gamma correction 242b, and themultiplexer 240b multiplexes a high Blue gamma correction 242c and ahigh RED gamma correction 242d. The multiplexer 244a multiplexes a lowWhite gamma correction 246a and a low Green gamma correction 246b, andthe multiplexer 244b multiplexes a low Blue gamma correction 246c and alow RED gamma correction 246d.

The driver output unit 270 includes a PMOS multiplexer 248 formultiplexing the outputs from the PMOS multiplexers 240a and 240b, and aNMOS multiplexer 250 for multiplexing the outputs from the NMOSmultiplexers 244a and 244b. Based on the image data and a colorselection, one of the low gamma correction and the high gamma correctionfor the selected color is selected.

The driver output unit 270 includes a DAC that is divided into separatecomponents; a PMOS component 252 (“PMOS DAC” in FIG. 8) for the highvoltage level of the gamma corrections and a NMOS component 254 (“NMOSDAC” in FIG. 8) for the low voltage level of the gamma corrections. ThePMOS component 252 includes a PMOS decoder and receives the output fromthe multiplexer 248. The NMOS component 254 includes a NMOS decoder andreceives the output from the multiplexer 250. The reference voltage fromthe gamma correction is selected based on the dynamic range of the NMOSand PMOS decoders in the components 252 and 254.

The PMOS and NMOS decoders in the components 252 and 254 operate on anoutput from a multiplexer 256 for multiplexing a White/Blue register258a and a Green/Red register 258b. The White/Blue register 258a storesimage data for White/Blue. The Green/Red register 258b stores image datafor Green/Red. In the RGBW structure, each data line carries data fortwo different colors. In this example, one data line carries data forWhite and Blue, and the other data line carries data for Green and Red.In one row, a data line is connected, for example, to White pixels(Green pixels) while during the next row it is connected to Blue pixels(Red pixels). As a result, the register 258a used for White and Bluedata is shared, and the register 258b used for Green and Red is shared.

The driver output unit 270 includes a CMOS multiplexer 260 formultiplexing the outputs from the PMOS and NMOS decoders in thecomponents 252 and 254. The multiplexer 260 is operated by a multiplexer262 for multiplexing bit signals G/R[i] and W/B[k]. W/B[k] (G/R[j]) is abit that defines when to use which part of the gamma for White or Blue(Green or Red). The bit W/B[k (G/R[j]) is generated based on theWhite/Blue register 258a (Green/Red register 258b) and predefined gammavalues for White and Blue (Green and Red). The multiplexer 260 providesa source driver output 264.

When the bit signal W/B[k] is active, the source driver 192 outputs thesource driver output 264 based on the high White gamma correction, thelow White gamma correction, the high Blue gamma correction, the lowWhite gamma correction or the low Blue gamma correction.

A demultiplexer 272 is employed in the panel 270 side to demultiplex thedriver output 264 from the source driver 232. The demultiplexer 272 isimplemented using, for example, thin film transistors, on the panel 270.The outputs from the demultiplexer 272 are couples to two data lines 274and 276. The demultiplexer 272 is controlled by a control signalassociated with the color selection. Based on the output from thedemultiplexer 272, one of two data lines 274 and 276 is active. Thedriver output 264 is demultiplexed 272 on the panel 270 side and goes todifferent subpixels (i.e., White subpixel, Blue subpixel, Greensubpixel, Red subpixel).

In the source driver 232, one PMOS decoder 254 is used for the higherrange and one NOMS decoder 254 for the lower range of the voltage. Thus,the area will be reduced by using twice less transistors than a CMOSdecoder.

In the panel 270, instead of having four Red subpixel, Green subpixel,Blue subpixel, and White subpixel side by side, they are configured in aquad arrangement where two subpixels for two colors are in one row andthe other two colors are in the other row. In this example, one dataline 274 carries data for White and Blue subpixels 278a and 278b, andthe other data line 276 carries data for Green and Red subpixels 278cand 278d, as shown in FIG. 9. The subpixels are divided into two rowsand two columns. Thus the source driver provides data for two subpixelsat a time.

Referring to FIG. 10, there is illustrated a system 280 having a sourcedriver 282, a panel 320 having pixels, and external gamma buffer area290. The system 280 is applied to RGB pixel structure. Multiple gammacorrections for Red, Green and Blue are multiplexed in the externalbuffer area 290. The external gamma buffer area 290 is located externalto the source driver area 282 (e.g., external to the source driver IC).The gamma voltages are generated externally and applied to the sourcedriver 282 through buffers in the external gamma buffer area 290. On thedisplay side 320, a demultiplexing is used to provide data for eachcolor. One of ordinary skill in the art would appreciate that the sourcedriver 282, the external gamma buffer area 290 and the panel 320 mayinclude components not shown in FIG. 10.

A PMOS multiplexer 292 is employed in the external gamma buffer area 290for high voltage level of gamma corrections, and a NMOS multiplexer 294is employed in the external gamma buffer area 290 for low voltage levelof gamma corrections. The multiplexer 292 multiplexes a high Red gammacorrection 296a, a high Green gamma correction 296b and a high Bluegamma correction 296c, and the multiplexer 294 multiplexes a low Redgamma correction 298a, a low Green gamma correction 298b and a low Bluegamma correction 298c. The gamma corrections 296a, 296b and 296ccorrespond to the gamma corrections 198a, 198b and 198c of FIG. 7,respectively and are located outside the source driver 282. The gammacorrections 298a, 298b and 298c correspond to the gamma corrections202a, 202b and 202c of FIG. 7, respectively and are located outside thesource driver 282. The PMOS and NMOS multiplexers 292 and 294 correspondto the multiplexers 196 and 200 of FIG. 7, respectively and are locatedoutside the source driver 282. The outputs from the PMOS and NMOSmultiplexers 292 and 294 are provided to the source driver 282.

The source driver 282 includes a driver output unit 284. The driveroutput unit 284 includes a DAC that is divided into separate components:a PMOS component 300 (“PMOS DAC” in FIG. 10) and a NMOS component 302(“NMOS DAC” in FIG. 10). The PMOS and NMOS components 300 and 302correspond to the PMOS and NMOS components 204 and 206 of FIG. 7,respectively. The PMOS component 300 includes a PMOS decoder andreceives the output from the multiplexer 292. The NMOS component 302includes a NMOS decoder and receives the output from the multiplexer294. The PMOS and NMOS decoders in the components 300 and 302 operate onan output from a multiplexer 304 for multiplexing a Red register 306a,Green register 306b and Blue register 306c. The resisters 306a, 306b and306b correspond to the registers 210a, 210b and 210c of FIG. 7,respectively.

The driver output unit 284 includes a CMOS multiplexer 308 formultiplexing the outputs from the PMOS and NMOS components 300 and 302.The multiplexer 308 is operated by a multiplexer 310 for multiplexingbit signals R[j], G[i] and B[k]. The multiplexers 308 and 310 correspondto the multiplexers 212 and 214 of FIG. 7, respectively. The multiplexer308 outputs a single source driver output 316.

A demultiplexer 322 is employed on the panel 320 side to demultiplex thedriver output 264 from the source driver 282. The demultiplexer 322corresponds to the demultiplexer 182 of FIG. 5. The demultiplexer 322 isimplemented using, for example, thin film transistors, on the panel 320.The outputs from the demultiplexer 322 are couples to three data lines.The demultiplexer 322 is controlled by a control signal associated withthe color selection. Based on the output from the demultiplexer 322, oneof three data lines is active. The driver output 316 is demultiplexed322 on the panel 320 side and goes to different subpixels (i.e., Redsubpixel, Blue subpixel, Green subpixel).

In this example, the PMOS decoder component 300 is used for the higherrange and the NOMS decoder component 302 for the lower range of thevoltage. Thus, the source area will be reduced by using twice lesstransistors than that of a CMOS decoder. In addition, the gammas aremultiplexed and provided from the outside of the source driver 282 area,thus the number of inputs required for the gamma correction is reducedas well.

For small displays, the gamma correction is internally programmable. Thedata for gamma correction is stored in internal registers. To reduce thenumber of gamma registers, DAC resistive ladders and DAC decoders, thegamma registers are multiplexed, as shown in FIG. 11. For programmingeach color, the corresponding gamma color is assigned to the gammablock. Referring to FIG. 11, there is illustrated a system 330 having asource driver 332 and a panel 360 having pixels. The system is appliedto quad RGB pixel structure. Multiple gamma corrections for Red, Greenand Blue are multiplexed in the source driver 332. One of ordinary skillin the art would appreciate that the source driver 332 and the panel 360may include components not shown in FIG. 11.

The source driver 332 includes a driver output unit 334 having amultiplexer 340 for multiplexing a Red gamma register 342a, a Greengamma register 342b and a Blue gamma register 342c, each for storing thecorresponding gamma correction data. The gamma correction is internallyprogrammed (configurable), and the data for the gamma correction isstored in the resister. The driver output unit 334 includes a gammacircuit 344 for generating the gamma voltage based on its input signalsfrom the multiplexer 340 (i.e., data from the gamma resister 342a, 342b,342c). The gamma circuit 344 may be, for example, but not limited to, adigital potentiometer or a DAC.

The driver output unit 334 includes a CMOS DAC 346 that has a decoderand receives the output from the gamma correction 344. The DAC decoderin the DAC 346 operates on an output from a multiplexer 348 formultiplexing a Red register 350a, a Green register 350b and a Blueregister 350c. The registers 350a, 350b and 350c correspond to theresisters 174a, 174b and 174c of FIG. 5, respectively. The driver output348 from the DAC decoder 346 is demultiplexed at a demultiplexer 362 inthe panel 360 and goes to different subpixels (e.g., Red subpixel, Greensubpixel and Blue subpixel). The demultiplexer 362 is implemented using,for example, thin film transistors, on the panel 360.

For further improving the source driver area, the DAC is divided intoNMOS and PMOS decoders as shown in FIG. 12. Referring to FIG. 12, thereis illustrated a system 370 having a source driver 372 and a panel 420having pixels. The system 370 is applied to RGB pixel structure.Multiple gamma corrections for Red, Green and Blue are multiplexed inthe source driver 372. One of ordinary skill in the art would appreciatethat the source driver 372 and the panel 420 may include components notshown in FIG. 12.

The source driver 372 includes a driver output unit 374 having amultiplexer 380 for multiplexing a Red gamma register 382a, a Greengamma register 382b and a Blue gamma register 382c. The gamma registers382a, 382b and 382c correspond to the gamma resisters 342a, 342b and342c of FIG. 11, respectively. The driver output unit 374 includes ahigh gamma circuit 384 and a low gamma circuit 386. The high gammacircuit 384 generates a high gamma voltage based on its input signalsfrom the multiplexer 380 (i.e., data from the gamma resister 382a, 382b,382c). The low gamma circuit 386 generates a low gamma voltage based onits input signals from the multiplexer 380 (i.e., data from the gammaresister 382a, 382b, 382c). Each of the gamma circuits 384 and 386 maybe, for example, but not limited to, a digital potentiometer or a DAC.

The driver output unit 374 includes PMOS and NMOS components 390 and392. The PMOS component 390 includes a PMOS decoder and is provided forthe high gamma 384. The NMOS component 392 includes a NMOA decoder andis provided for the low gamma 386. The PMOS and NMOS components 390 and392 correspond to the PMOS and NMOS components 204 and 206 of FIG. 7.The PMOS and NMOS decoders in the components 390 and 392 operate on anoutput from a multiplexer 394 for multiplexing a Red register 396a, aGreen register 396b and a Blue register 396c. The registers 396a, 396band 396c correspond to the resisters 174a, 174b and 174c of FIG. 5(210a, 210b and 210c of FIG. 7), respectively.

The driver output unit 374 includes a CMOS multiplexer 400 formultiplexing the outputs from the PMOS and NMOS decoders in thecomponents 390 and 392. The multiplexer 400 is operated by a multiplexer402 for multiplexing bit signals R[j], G[i] and B[k]. The bit signalsR[j], G[i] and B[k] correspond to the bit signals R[j], G[i] and B[k] ofFIG. 8. The multiplexer 400 outputs a source driver output 404.

A demultiplexer 422 is employed on the panel 420 side to demultiplex thedriver output 404 from the source driver 372. The demultiplexer 422corresponds to the demultiplexer 182 of FIG. 5. The demultiplexer 422 isimplemented using, for example, thin film transistors, on the panel 420.The outputs from the demultiplexer 422 are couples to three data lines.The demultiplexer 422 is controlled by a control signal associated withthe color selection. Based on the output from the demultiplexer 422, oneof three data lines is active. The driver output 404 is demultiplexed422 on the panel 420 side and goes to different subpixels (i.e., Redsubpixel, Blue subpixel, Green subpixel).

To develop muxing in a source driver, data for each color is multiplexedas shown in FIG. 13. FIG. 13 illustrates a source driver 450 forscanning a panel for a conventional display system. The source driver450 includes a shift register unit 452 and a latch unit 456. The shiftregister unit 452 includes a plurality of shift registers 454a-454d, andreceives a latch signal. The latch unit 456 includes a plurality oflatch circuits 458a-458d that are employed for the shift registers454a-454b, respectively. Each latch circuit 458a, 458b, 458c, 458dlatches a digital image signal in response to the latch signal from thecorresponding shift register. The outputs from three latch circuits458a, 458b and 458c are multiplexed by a multiplexer 460 to output R, G,B image signals. The data for each color is multiplexed 460. A DAC 462includes a decoder for decoding the output from the multiplexer 460 tooutput analog image signals.

To further reduce the source area, the latch unit 456 is replaced withshift registers as shown in FIG. 14. Referring to FIG. 14, there isillustrated a source driver 480 for a display system. The source driver480 includes a first stage shift register unit 482, a second stage latchand shift unit 486, and a DAC unit. The multiplexer 460 of FIG. 13 isnot implemented in the source driver 480 side. The shift register unit482 includes a plurality of shift registers, and each receives a latchsignal. The latch and shift unit 486 includes a plurality of latch andshift registers that are employed for the shift registers in the shiftregister unit 482, respectively. In FIG. 14, four shift registers484a-484d are shown as an example of the components of the shiftregister unit 482. In FIG. 14, four latch and shift registers 488a-488dare shown as an example of the components of the latch and shift unit486. In FIG. 14, one DAC 490 is shown as an element of the DAC unit. TheDAC 490 has a decoder. The DAC 490 is coupled to the latch and shiftregister 488c, which decodes its input and outputs a source driveroutput 492.

It will be appreciated by one of ordinary skill in the art that thenumber of the shift registers and the number of the latch and shiftregisters are not limited to four and may vary. It will be appreciatedby one of ordinary skill in the art that the source driver 480 mayinclude components not illustrated in FIG. 14. It will be appreciated byone of ordinary skill in the art that the DAC unit of the source driver480 may include more than one DAC. In one example, the DAC unit includesa plurality of DACs connected in M intervals.

Each latch and shift register in the second stage latch and shift unit486 can copy its input signal and keep it intact till the nextactivation signal. The input signal to the latch and shift register maycome from the corresponding first stage shift register or the previouslatch and shift register in the chain. As a result, the latch and shiftregister can store the data for a row from the first stage shiftregister or it can shift its own data to the next units. For example,the latch and shift register 488a latches a digital image signal inresponse to an activation signal from the corresponding shift register484a. The latched signal is shifted to the next latch and shift register488b.

After the input signal for a row is stored in the shift register unit482, the second stage latch unit 486 is activated and copies the signalsfrom the shift register unit 482. After that, the second stage latchunit 486 shifts the data one by one to the DACs connected in M intervalsconnect to the latch unit where M defines the muxing order.

After the first color data is programmed, the latch data is shifted bythe number of required bits so that the second data is stored in thelatch 488c connected to the DAC 490. This operation is executed forother colors as well until all the colors are programmed. Thisimplementation results in a simpler routing and smaller die area. Itwill be appreciated by one of ordinary skill in the art that a panelside may have a demultiplexer for demultiplexing the source driver 480output associated with the M multiplexing operation. It will beappreciated by one of ordinary skill in the art that the source driver480 is applicable to monochrome displays.

Referring to FIG. 15, there is illustrated a source driver 500 for adisplay system. To develop DAC decoders, high voltage fabricationprocess is used, which results in large die area. Instead of a havingone gamma curve that covers the entire output voltage rage (e.g. 0 to15), the source driver 500 uses a plurality of smaller offset gammacurve segments (sections) at lower voltage range, which are extractedfrom different part of the complete gamma curve.

The source driver 500 includes a gamma block 502 for changing the color(gray scale) mapping for a display, a resistive ladder 504 forgenerating reference voltages, and an overlapping multiplexer block 506for the offset gamma curve sections.

The overlapping multiplexer block 506 includes a plurality ofmultiplexers, each for multiplexing reference voltages for differentcolors. In FIG. 15, three multiplexers 508a, 508b and 508c are shown asan example of components of the overlapping multiplexer block 506. Theadjacent multiplexer covers different range of the output voltage,having the beginning and the end of the range. However, the end of onerange in one multiplexer and the beginning of the other range in theadjacent multiplexer overlap each other. The overlapping providesflexibility in achieving different gamma curve. The same inputs arebeing used for both multiplexers.

The source driver 500 includes a DAC decoder section that is segmentedinto a plurality of low voltage decoders for the offset gamma curvesections. In FIG. 15, the three low voltage decoders 510a, 510b and 510care shown as the elements of the DAC decoder, each operating at lowvoltage. The two adjacent decoders share a small portion of theirdynamic range. A programmable decoder 512 defines the border of eachdecoder 510a-510c according to the gamma curves. This allows for havingdifferent gamma curves for different applications.

In FIG. 16A, an example of a main gamma curve is illustrated. The maingamma curve 530 of FIG. 16A has a range from 0 to 10V. In FIG. 16B, themain gamma curve 530 of FIG. 16A is segmented into a plurality of offsetgamma curve sections 540, 542 and 544. Each offset gamma curve sectionhas a shape corresponding to that of the same section of the main gammacurve 530, and has a voltage range 0 to 5V. The gamma curve section 542is offset by −5V. The gamma curve section 542 is offset by −10V. Usingthe offset gamma curve sections, the internal circuits associated withthe gamma corrections are offset to lower voltage. The gamma curvesection may be internally programmed or input from an external area ordevice. The display system may include a module for programming/definingoffset gamma curve sections. This module may be integrated or operate inconjunction with the programmable decoder 512.

Referring to FIGS. 15 and 16B, the multiplexer 508a is allocated for oneoffset gamma curve section (e.g., 540 of FIG. 16B) and the low voltagedecoder 510a uses that offset gamma curve section. The multiplexer 508bis allocated for another offset gamma curve section (e.g., 542 of FIG.16B) and the low voltage decoder 510b uses that offset gamma curvesection. The multiplexer 508c is allocated for the other offset gammacurve section (e.g., 544 of FIG. 16B) and the low voltage decoder 510cuses that offset gamma curve section. The low voltage decoders 510a,510b and 510c are programmable.

The source driver 500 includes an output buffer 516. The output buffer516 outputs a source driver output 520 based on the output from thedecoder and the offset voltage.

Based on the pixel circuit data, one offset gamma curve section with itscorresponding decoder is being selected. Then the data is passed to theoutput buffer 516. In order to create the required voltage, the createdvoltage is being shifted up at the output buffer 516. If a voltage isselected from the second gamma curve section 542 of FIG. 16B, it will beoffset by 5 V at the output buffer 516 to cover for the original offset.

Each segment is in its own well so that the body bias can be adjustedaccordingly. The decoder can be implemented in low voltage process,leading to smaller die area (over three times saving).

Referring to FIG. 17, there is illustrated an example of a displaysystem 600. The system 600 includes a controller 602, a source driver IC604, a gate driver IC 606, and a panel 608. The gate driver 606 mayinclude the gate driver 102 of FIGS. 1A-1B or the gate driver 132 ofFIGS. 3A-3B. The panel 608 includes a pixel array having a plurality ofpixels (or subpixels) 610 and a demultiplexer 612. The demultiplexer 612may include the demultiplexer 112 of FIGS. 1A-1B or the demultiplexer142 of FIGS. 3A-3B. The controller 602 controls the source driver 604and the gate driver 606. The controller 602 also generates controlsignals 614 to operate the demultiplexer 612, which may correspond tothe control signals CTRL(k) of FIGS. 1A or 3A. The demultiplexer 612 isimplemented using, for example, thin film transistors, on the panel 608.

Referring to FIG. 18, there is illustrated an example of a displaysystem 630. The system 530 includes a controller 632, a source driver IC634, a gate driver IC 636, and a panel 638. The source driver 632 mayinclude the source driver 162 of FIG. 5, 192 of FIG. 7, 232 of FIG. 8,282 of FIG. 10, 332 of FIG. 11 or 372 of FIG. 12. The panel 638 includesa pixel array having a plurality of pixels (or subpixels) 610 and ademultiplexer 642. The demultiplexer 642 may include the demultiplexer182 of FIG. 5, 222 of FIG. 7, 272 of FIG. 8, 322 of FIG. 10, 362 of FIG.11 or 422 of FIG. 12. The controller 632 controls the source driver 634and the gate driver 636. The controller 632 also generates controlsignals 644 to operate the demultiplexer 632. The demultiplexer 642 isimplemented using, for example, thin film transistors, on the panel 638.The system 630 may includes the external gamma 290 of FIG. 10.

Referring to FIG. 19, there is illustrated an example of a displaysystem 660 having the source driver elements of FIG. 14 or FIG. 15. Thesystem 660 includes a controller 662, a source driver IC 664, a gatedriver IC 666, and a panel 668. The panel 668 includes a pixel arrayhaving a plurality of pixels (or subpixels) 610. The controller 662controls the source driver 664 and the gate driver 666. The controller662 controls, for example, the shift register unit 482 and the latch andshift unit 486 of FIG. 14 or the overlapping multiplexer block 506 andthe low voltage decoders 510a-510b of FIG. 15.

In the above example, the gate drivers and the source drivers aredescribed separately. However, one of ordinary skill in the art wouldappreciate that any of the gate drivers of FIGS. 1A and 3B can be usedwith the source drivers of FIGS. 6-15.

What is claimed is:
 1. A drive system for an a light emitting device(LED) display panel having a multiplicity of LED pixels arranged in rowsand columns, each of said LED pixels having a drive transistor thatincludes a gate, a source and a drain and each of said LED pixelsfurther having an LED coupled to said drive transistor, comprising: agate driver having at least one address cell providing a single gatedriver output for multiple rows of pixels of said LED display panel, agate driver multiplexer and a demultiplexer that includes multipleswitch blocks coupled to the gate driver and controllably coupling saidsingle gate driver output to said multiple rows of pixels in sequence sothat whenever such that when a selected one of said multiple rows isconnected to said single gate driver output, all the other said multiplerows are disconnected from said single-game single-gate driver output.2. A display system according to claim 1, wherein the gate driver outputunit comprises: at least one multiplexer, the multiplexer formultiplexing driver signals to provide the single gate driver output. 3.A display system according to claim 2, wherein the panel comprises: ademultiplexer having a plurality of switch blocks for activating thefirst lines multiple rows, each switch block receiving outputs from theat least one multiplexer.
 4. A method of driving a display panel havinga multiplicity of pixels arranged in rows and columns, each of saidpixels having a drive transistor that includes a gate, a source and adrain, said method comprising: multiplexing driver signals to generate asingle gate driver signal; providing a single gate driver signal formultiple rows of said pixels of said display panel, demultiplexing thesingle gate driver signal by controllably coupling said single gatedriver signal to selected ones of said multiple rows of pixels insequence, and controllably disconnecting said gate driver signal fromsaid multiple rows of pixels to which said single gate driver signal isnot coupled.